27 research outputs found

    Compact Implementations of BLAKE-32 and BLAKE-64 on FPGA

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    We propose compact architectures of the SHA-33 candidates BLAKE-32 and BLAKE-64 for several FPGA families. We harness the intrinsic parallelism of the algorithm to interleave the computation of four instances of the GiG_i function. This approach allows us to design an Arithmetic and Logic Unit with four pipeline stages and to achieve high clock frequencies. With careful scheduling, we completely avoid pipeline bubbles. For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. We show for instance that a fully autonomous implementation of BLAKE-32 on a Xilinx Virtex-5 device requires 56 slices and two memory blocks

    A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function ECHO

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    We propose a compact coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function ECHO on Virtex-55 and Virtex-66 FPGAs. Our architecture is built around a 88-bit datapath. The Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and ECHO at all levels of security. Thanks to a careful organization of AES and ECHO internal states in the register file, we manage to generate all read and write addresses by means of a modulo-1616 counter and a modulo-256256 counter. A fully autonomous implementation of ECHO and AES on a Virtex-55 FPGA requires 193193 slices and a single 3636k memory block, and achieves competitive throughputs. Assuming that the security guarantees of ECHO are at least as good as the ones of the SHA-33 finalists BLAKE and Keccak, our results show that ECHO is a better candidate for low-area cryptographic coprocessors. Furthermore, the design strategy described in this work can be applied to combine the AES and the SHA-33 finalist {G}røstl

    A Compact FPGA Implementation of the SHA-3 Candidate ECHO

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    We propose a compact architecture of the SHA-3 candidate ECHO for the Virtex-5 FPGA family. Our architecture is built around a 8-bit datapath. We show that a careful organization of the chaining variable and the message block in the register file allows one to design a compact control unit based on a 4-bit counter, an 8-bit counter, and a simple Finite State Machine. A fully autonomous implementation of ECHO on a Xilinx Virtex-5 FPGA requires 127127 slices and a single memory block to store the internal state, and achieves a throughput of 7272Mbps

    A Low-Area Unified Hardware Architecture for the AES and the Cryptographic Hash Function Grøstl

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    This article describes the design of an 8-bit coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function Grøstl on several Xilinx FPGAs. Our Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Grøstl at all levels of security. Thanks to a careful organization of AES and Grøstl internal states in the register file, we manage to generate all read and write addresses by means of a modulo-128 counter and a modulo-256 counter. A fully autonomous implementation of Grøstl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput. Assuming that the security guarantees of Grøstl are at least as good as the ones of the other SHA-3 finalists, our results show that Grøstl is the best candidate for low-area cryptographic coprocessors

    Compact Hardware Implementations of ChaCha, BLAKE, Threefish, and Skein on FPGA

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    The cryptographic hash functions BLAKE and Skein are built from the ChaCha stream cipher and the tweakable Threefish block cipher, respectively. Interestingly enough, they are based on the same arithmetic operations, and the same design philosophy allows one to design lightweight coprocessors for hashing and encryption. The key element of our approach is to take advantage of the parallelism of the algorithms to deeply pipeline our Arithmetic an Logic Units, and to avoid data dependencies by interleaving independent tasks. We show for instance that a fully autonomous implementation of BLAKE and ChaCha on a Xilinx Virtex-6 device occupies 144 slices and three memory blocks, and achieves competitive throughputs. In order to offer the same features, a coprocessor implementing Skein and Threefish requires a substantial higher slice count

    Correction to "Influence of Dust and Black Carbon on the Snow Albedo in the NASA Goddard Earth Observing System Version 5 Land Surface Model"

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    The website information describing the forcing meteorological data used for the land surface model (LSM) simulation, which were observed at an Automated Meteorological Station CAWS) at the Sapporo District Meteorological Observatory maintained by the Japan Meteorological Agency (JMA), was missing from the text. The 1-hourly data were obtained from the website of Kisyoutoukeijouhou (Information for available JMA-observed meteorological data in the past) on the website of JMA (in Japanese) (available at: http://www.jma.go.jpijmaimenulreport.html). The measurement height information of 59.5 m for the anemometer at the Sapporo Observatory was also obtained from the website of JMA (in Japanese) (available at: http://www.jma.go.jp/jma/menu/report.html). In addition, the converted 10-m wind speed, based on the AWS/JMA data, was further converted to a 2-m wind speed prior to its use with the land model as a usual treatment of off-line Catchment simulation. Please ignore the ice absorption data on the website mentioned in paragraph [15] which was not used for our calculations (but the data on the website was mostly the same as the estimated ice absorption coefficients by the following method because they partially used the same data by Warren [1984]). We calculated the ice absorption coefficients with the method mentioned in the same paragraph, for which some of the refractive index data by Warren [1984] were used and then interpolated between wavelengths, and also mentioned in paragraph [20] for the visible (VIS) and near-infrared (NIR) ranges. The optical data we used were interpolated between wavelengths as necessary

    Impacts of Asian dust storm associated with the stratosphere-to-troposphere transport in the spring of 2001 and 2002 on dust and tritium variations in Mount Wrangell ice core, Alaska

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    The relation of interannual connection between Asian dust outbreaks and stratosphere-to-troposphere transport (STT) in spring was suggested by the dust and tritium variations in the Mount Wrangell ice core, Alaska in Yasunari et al. (2007). However, these impacts on the ice core site in each event scale have not been investigated. Hence, the present paper focuses on the material transport and deposition processes for further understanding these impacts oil the ice core. The variations in dust and tritium concentrations in spring in an ice core taken at Mt. Wrangell, Alaska are explained by meteorological analysis and simulation of trajectories associated with Asian dust outbreaks and STT. Material transport and deposition at Mt. Wrangell are examined in two contrasting years (2001 and 2002). Dust and tritium concentrations both reached peak values in the early spring of 2002, while the dust peak occurred in early spring and the tritium peak occurred in late spring in 2001. Six severe East Asian transpacific dust storms over this period are modeled by forward trajectory and meteorologically analyzed. It is found that 5 of 6 events contributed to the ice core record in Alaska. Stratospheric air is also transported to the ice core site in most cases. Tritium deposition is found to have been suppressed in the cases of the 2001 dust Storms due to lack of snowfall at appropriate times. Taken the detailed transport and deposition processes after the severe dust storms with atmospheric circulations into account, we can well explain spring dust and tritium variations in the Mount Wrangell ice core
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